1. Field of the Invention
The present invention relates to a fabricating technology of a semiconductor integrated circuit. More particularly, it relates to a technology effectively adaptable for fabricating process a semiconductor integrated circuit with a step of forming a ruthenium electrode of a capacitor with high-k material by a chemical vapor deposition (CVD) method using an organoruthenium (Ru) compound as a precursor.
2. Description of the Related Art
A DRAM (Dynamic Random Access Memory) is so configured that each one of its memory cells comprising a selective transistor and an information storage capacitor (below, referred to as a capacitor) are arranged in a matrix on a semiconductor substrate. The capacitance of the memory cell capacitor needs to be increased in density for configuring a large capacity DRAM. A method teaches using a tantalum pentoxide (Ta2O5) film with a high dielectric constant as a dielectric film of a capacitor in JP-A-244364/1994.
In the foregoing publication, a polysilicon is adapted as a bottom electrode, and a process is adopted in which a silicon nitride film is formed on the surface by a thermal nitriding method using ammonia in order to prevent electrode oxidation. However, since the silicon nitride film has a lower dielectric constant than the tantalum pentoxide film, the total capacitor capacitance is reduced. Further, an oxide dielectric, such as the tantalum pentoxide film, is required to undergo film formation and post annealing in an oxidation atmosphere at a high temperature of at least 300° C. to 700° C. for improving the electrical characteristics thereof. In the step, the silicon nitride film is oxidized to a silicon oxynitride (SiON) film with a relatively lower dielectric constant, which inevitably further decreases the capacitor's capacitance.
As such, a study has been done on a MIN (Metal Insulator Metal) structure using, as a bottom electrode material, platinum (Pt) which is relatively stable at a high temperature and in an oxidation atmosphere, ruthenium (Ru), or iridium (Ir) which holds electrical conductivity even if an oxide thereof is formed. In the MIM structure, an insulator with low dielectric constant is not formed in the interface between an electrode and a dielectric film, and hence it is possible to increase the density of the capacitor capacitance. Further more, out of these metals, ruthenium, which is excellent in micromachinability, is the most preferable material as a bottom electrode of the oxide dielectric.
The present inventors have studied the application of the capacitor made up of a ruthenium electrode and a high-k dielectric material described above to a large capacity semiconductor integrated circuit, such as a 256 M bit DRAM or 1 G bit DRAM. For such a large capacity DRAM, the electrode is required to be formed three dimensionally in order to provide the required capacitor's capacitance. The present inventors have conducted a study on a technology of forming a ruthenium electrode by a Chemical Vapor Deposition (CVD) method. Below, the technology of forming a capacitor of the invention is described, and the problems and deficiencies thereof are pointed out.
A method in which a deep hole is processed in a silicon dioxide film during a step of sub-micron patterning from its surface, and then a bottom electrode of ruthenium is deposited to form a three dimensional structure is described by reference to FIGS. 16(a) to 16(e) as follows. All the figures denote cross sectional views. Further, only a capacitor forming area is shown, and other areas are omitted.
First, a silicon dioxide film having a through hole 7 in which a plug 1 made of a polysilicon (Poly-Si) and a barrier layer 19 made of, for example, titanium nitride (TiN) are buried. On an interlayer insulator of a plug region 2 made of the silicon dioxide film, an interlayer insulator of a capacitor region 3 made of, for example, a silicon dioxide film and with a film thickness of 1000 nm, is deposited (FIG. 16(a)).
The laminated plug (the plug 1 and the barrier layer 19) is formed for ensuring the electrical connection between a diffusion layer of a selective transistor (not shown) and the bottom electrode of a capacitor. The barrier layer 19 on top of the plug 1 is necessary for inhibiting the silicidization reaction between the bottom electrode of ruthenium and the Poly-Si plug 1.
Then, by using a known photolithography method and a dry etching method, the interlayer insulator of the capacitor region 3 is processed to the surface of the interlayer insulator of plug region 2 such that the resulted window is in a form of cylinder, elliptical cylinder, or rectangle (as a deep hole 8) (FIG. 16(b)).
Then, a ruthenium film 4a of 30 nm thick is deposited in the deep hole 8. The ruthenium film 4a is deposited by a CVD method using, for example, Ru(C5H4C2H5)2 as a precursor (FIG. 16(c)).
Then, in order to isolate the adjacent capacitors from each other, the ruthenium film 4a deposited on the top face of the interlayer insulator of the capacitor region 3 is removed by sputtering etching, thereby forming a bottom electrode of ruthenium 4 having a three dimensional structure in the deep hole 8 (FIG. 16(d)).
Then, a high-k dielectric film 5 of 10 nm thick made of, for example, tantalum pentoxide (Ta2O5) is deposited thereon by a CVD method. Subsequently, annealing for the crystallization thereof is performed at 400° C. to 700° C., and then, a top electrode 6 made of, for example, ruthenium is deposited thereon by a CVD method, thereby completing a capacitor (FIG. 16(e)).
The resistance of the laminated plug connecting between the bottom electrode of ruthenium 4 and the selective transistor is determined for the capacitor formed in the foregoing manner. As a result, they are not well conducted. Further, the leakage current of the capacitor is determined by applying a voltage of +1 V to the top electrode 6 of the capacitor, which incurs a leakage current of 3×10−3 A/CM2 is flown therethrough, i.e. the capacitor is not well insulated. According to the cross section of the capacitor closely observed by means of a transmission electron microscope (TEM), an oxide layer of TiN, ex. titanium dioxide (TiO2), is formed in the interface between the bottom electrode of ruthenium 4 and the barrier layer 19 such that peeling occurs locally. For comparison, after forming the bottom electrode of ruthenium 4 (after FIG. 16(d)), one-minute annealing at 500° C. is performed in an inert gas without forming the high-k dielectric film (tantalum pentoxide film) 5. However, even this process similarly causes the capacitor being poorly insulated. Further, as a result of the transmission electron microscope (TEM) analysis, peeling due to shrinkage of the ruthenium film itself happens. An X-ray diffraction diagram of the structure shows a peak corresponding to TiO2 and a slight peak corresponding to RuO2 other than the peak corresponding to ruthenium crystals. Consequently, it is conceivable that the oxygen contained in slight amounts in the bottom electrode of ruthenium 4 formed with the CVD method causes oxidation of the barrier layer 9. Further, it is also conceivable that the thermal shrinking of the ruthenium film is caused by oxygen diffusing into the barrier layer 9.
On the other hand, similarly, the TEM observation indicated that the crystal grain size and the surface morphology of the bottom electrode of ruthenium 4 change largely after annealing for crystallizing the high-k dielectric film (tantalum pentoxide film) 5. After forming the bottom electrode of ruthenium 4, the crystal grain size is about 10 nm, and a largely uneven surface is observed. However, the tantalum pentoxide film is then formed with the CVD method, and subjected to annealing for crystallization at a temperature of 650° C. As a result, the crystal grain size changes. Consequently, it is conceivable that the capacitor is not well insulated because the bottom electrode of ruthenium 4 is deformed during the annealing for crystallization.